These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers
with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus
or from the internal storage registers. OEAB and OEBA\ control pins are provided to control the transceiver functions. SAB and
SBA control pins are provided to select either real-time or stored data transfer.
Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling
OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will remain at its last state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
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