See datasheet for actual packaging/pinout drawings

Package | PIN:

ZJB | 160


I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

TI Store Price:

1 - 9 $ 14.18
10 - 24 $ 13.19
25 - 99 $ 12.73
100 - 249 $ 11.12
250 - 499 $ 10.58
500 - 749 $ 9.74
750 - 999 $ 8.74
1000 - 9999 $ 8.71
  View datasheet for 74SSTUB32865AZJBR View product folder for 74SSTUB32865AZJBR

Adjust your quantity during checkout

74SSTUB32865AZJBR-28-Bit to 56-Bit Registered Buffer with Address-Parity Test

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to stacked 18 SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads.

All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (PTYERR) output.

The 74SSTUB32865A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low.

The 74SSTUB32865A accepts a parity bit from the memory controller on the parity bit (PARIN) input, compares it with the data received on the DIMM-independent D-inputs (D0-D21) and indicates whether a parity error has occurred on the open-drain PTYERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.

The 74SSTUB32865A includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PARIN input of the device. Two clock cycles after the data are registered, the corresponding PTYERR signal is generated.

If an error occurs and the PTYERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the PTYERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before the device enters the low-power mode (LPM) and the PTYERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity check computation.

In a typical DDR2 RDIMM application, RESET is completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs are quickly driven low, relative to the time to disable the differential input receivers. However, when coming out of reset, the register quickly becomes active, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the 74SSTUB32865A outputs remain low, thus preventing glitches on the output.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except PTYERR. The LVCMOS RESET input must always be held at a valid logic high or low level.

The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1) and CSGateEN inputs. It gates the Qn outputs from changing states when the CSGateEN, DCS0, and DCS1 inputs are high. If the CSGateEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1 inputs are high, the device gates the PTYERR output from changing states. If either DCS0 or DCS1 is low, the PTYERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control, and when driven low forces the Qn outputs low, and the PTYERR output high. If the chip-select control functionality is not desired, then the CSGateEN input can be hardwired to ground, in which case, the setup-time requirement for DCS0 and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only, then the CSGateEN input should be pulled up to VCC through a pullup resistor.

The two VREF pins (A1 and V1) are connected together internally by a resistance of approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00