The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs.
It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega
Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both
edges of the output clock to be utilized while achieving a smaller package size. This converter
uses a differential, pipelined architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption and the external component count, while
providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes
951 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation
with reduced noise. A power-down feature reduces the power consumption to 15 mW while still
allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes
50 mW of power and has a faster wake-up time.
The differential inputs provide a full scale differential input swing equal to 2 times
the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can
be operated with an external reference.
Clock mode (differential versus single-ended) and output data format (offset binary
versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a
wide range of input clock duty cycles.
The ADC14V155 is pin-compatible with the ADC12V170. It is available in a 48-lead WQFN
package and operates over the industrial temperature range of −40°C to +85°C.
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