Features for the ADC32RF80EVM
- Onboard clock generation, or external clocking supported with LMK04828 generating SYSREF
- JESD204B data interface to simplify digital interface; compliant up to 10.8-Gbps lane rates
- Supports JESD204B subclass 1 for synchronization and compatibility
- Optional decimation filter outputs sample data at reduced sample rate for improved SNR
- On-chip dither to improve SFDR
Description for the ADC32RF80EVM
The ADC32RF80 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF80 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for each channel of the ADC is, by default, connected to a transformer input circuit, which can be connected to a 50-Ω single-ended signal source.
The clock reference input is provided via a transformer input and can be connected to a 50-Ω single-ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks.
Configuration register access is provided through the onboard USB connection and a Windows®-based GUI. An industry-standard JESD204B pin assignment on an FMC connector allows direct connection to the TSW14J56 Capture Card, as well as many commercially available FPGA development platforms.