ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit
125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of
interface lines, resulting in a compact 48-pin QFN package (7 mm × 7 mm) that allows for high
system integration density. The device includes 3.5 dB coarse gain option that can be used to
improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain
options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two
LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface)
and restrict it to less than 1 Gbps easing receiver design. The ADS622X also includes the
traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive
the bit clock. The bit clock is used to serialize the ADC data from each channel. In addition to
the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS
output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye-openings and improve signal integrity,
easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement
or straight binary.
ADS622X has internal references, but can also support an external reference mode. The
device is specified over the industrial temperature range (–40°C to 85°C).
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