See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

D | 16

Temp:

M (-55 to 125)

ECO Plan:

Green (RoHS & no Sb/Br)

CD74HC109M96


High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

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Texas Instruments CD74HC109M96

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

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