See datasheet for actual packaging/pinout drawings

Package | PIN:

PW | 16


M (-55 to 125)

ECO Plan:

Green (RoHS & no Sb/Br)

TI Store Price:

1 - 9 $ 0.57
10 - 24 $ 0.50
25 - 99 $ 0.45
100 - 249 $ 0.39
250 - 499 $ 0.35
500 - 749 $ 0.27
750 - 999 $ 0.21
1000 - 9999 $ 0.18
  View datasheet for CD74HC137PWR View product folder for CD74HC137PWR

Adjust your quantity during checkout

CD74HC137PWR-High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer with Address Latches

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High".

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00