The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage
synchronous down counter with a single output, which is active when the internal count is zero. The device
contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count (TC)\ output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)
output. Counting is inhibited when the terminal enable (TE)\ input is high. TC\ goes low when the count reaches
zero, if TE\ is low, and remains low for one full clock period.
When the synchronous preset enable (PE)\ input is low, data at the P0-P7 inputs are clocked into the counter on
the next positive clock transition, regardless of the state of TE\. When the asynchronous preset enable (PL)\ input
is low, data at the P0-P7 inputs asynchronously are forced into the counter, regardless of the state of the PE\, TE\,
or CP inputs. Inputs P0-P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset
(MR)\ input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of
any other input. The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except TE\ are high at the time of zero count, the counters jump to the maximum count, giving a
counting sequence of 10016 or 25610 clock pulses long.
The CD74HC40103 may be cascaded using the TE\ input and the TC\ output in either synchronous or ripple
mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds
comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.
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