The CD74HC93 and CD74HCT93 are high-speed silicon-gate
CMOS devices and are pin-compatible with low power
Schottky TTL (LSTTL). These 4-bit binary ripple counters
consist of four master-slave flip-flops internally connected to
provide a divide-by-two section and a divide-by-eight section.
Each section has a separate clock input (CP0\ and CP1\) to
initiate state changes of the counter on the HIGH to LOW
clock transition. State changes of the Qn outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes.
A gated AND asynchronous master reset (MR1 and MR2 is
provided which overrides both clocks and resets (clears) all
Because the output from the divide by two section is not
internally connected to the succeeding stages, the device
may be operated in various counting modes.
In a 4-bit ripple counter the output Q0 must be connected
externally to input CP1\. The input count pulses are applied
to clock input CP0\. Simultaneous frequency divisions of 2, 4,
8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs
as shown in the function table. As a 3-bit ripple counter the
input count pulses are applied to input CP1\.
Simultaneous frequency divisions of 2, 4, and 8 are available
at the Q1, Q2, Q3 outputs. Independent use of the first flip-flop
is available if the reset function coincides with the reset
of the 3-bit ripple-through counter.
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