See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

N | 16

Temp:

M (-55 to 125)

ECO Plan:

Pb-Free (RoHS)

CD74HCT112E


High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

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Texas Instruments CD74HCT112E

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.

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