The CDC2582 is a high-performance, low-skew, low-jitter clock
driver. It uses a phase-lock loop (PLL) to precisely align the
frequency and phase of the clock output signals to the differential
LVPECL clock (CLKIN, ) input
signals. It is specifically designed to operate at speeds from 50 MHz
to 100 MHz or down to 25 MHz on outputs configured as half-frequency
outputs. Each output has an internal 26- series resistor that
improves the signal integrity at the load. The CDC2582 operates at
The feedback input (FBIN) synchronizes the frequency of the output
clocks with the input clock (CLKIN, ) signals. One of the twelve output clocks must be fed
back to FBIN for the PLL to maintain synchronization between the
differential CLKIN and inputs and the outputs. The output used as feedback is
synchronized to the same frequency as the clock (CLKIN and ) inputs.
The Y outputs can be configured to switch in phase and at the same
frequency as differential clock inputs (CLKIN and ). Select (SEL1, SEL0) inputs
configure up to nine Y outputs, in banks of three, to operate at
one-half or double the differential clock input frequency, depending
upon the feedback configuration (see Tables 1
and 2). All output signal duty cycles are adjusted to 50% independent
of the duty cycle at the input clocks.
Output-enable () is provided
for output control. When is
high, the outputs are in the low state. When is low, the outputs are active.
negative-edge triggered and can be used to reset the outputs
operating at half frequency. TEST is used for factory testing of the
device and can be used to bypass the PLL. TEST should be strapped to
GND for normal operation.
Unlike many products containing a PLL, the CDC2582 does not
require external RC networks. The loop filter for the PLL is included
on chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2582 requires a
stabilization time to achieve phase lock of the feedback signal to
the reference signal. This stabilization time is required following
power up and application of a fixed-frequency, fixed-phase signal at
CLKIN and , as well as
following any changes to the PLL reference or feedback signal. Such
changes occur upon change of SEL1 and SEL0, enabling the PLL via
TEST, and upon enable of all outputs via .
The CDC2582 is characterized for operation from 0°C to
detailed description of output configurations
The voltage-controlled oscillator (VCO) used in the CDC2582 has a
frequency range of 100 MHz to 200 MHz, twice the operating frequency
range of the CDC2582 outputs. The output of the VCO is divided by 2
and by 4 to provide reference frequencies with a 50% duty cycle of
one-half and one-fourth the VCO frequency. SEL0 and SEL1 determine
which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the
PLL. The VCO operates such that the frequency of this output matches
that of the CLKIN/ signals. In
the case that a VCO/2 output is wired to FBIN, the VCO must operate
at twice the CLKIN/frequency,
resulting in device outputs that operate at the same or one-half the
CLKIN/ frequency. If
a VCO/4 output is wired to FBIN, the device outputs operate at the
same or twice the CLKIN/frequency.
output configuration A
Output configuration A is valid when any output configured as a
1× frequency output in Table 1 is fed back to FBIN. The
frequency range for the differential clock input is 50 MHz to 100 MHz
when using output configuration A. Outputs configured as 1/2×
outputs operate at half the input clock frequency, while outputs
configured as 1× outputs operate at the same frequency as the
differential clock input.
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a
1× frequency output in Table 2 is fed back to FBIN. The
frequency range for the differential clock inputs is 25 MHz to 50 MHz
when using output configuration B. Outputs configured as 1×
outputs operate at the input clock frequency, while outputs
configured as 2× outputs operate at double the frequency of the
differential clock inputs.
NOTE: n = 1, 2, 3
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