The CDCL6010 is a high-performance, low phase noise clock multiplier, distributor, jitter cleaner, and low skew buffer. It effectively cleans a noisy system clock with a fully-integrated low noise Voltage Controlled Oscillator (VCO) that operates in the 1.2GHz–1.275GHz range. (Note that the LC oscillator oscillates in the 2.4GHz–2.55GHz range. The frequency is predivided by 2 before the post-dividers P0 and P1.)

The output frequency (F_{OUT}) is synchronized to the frequency of the input clock (F_{IN}). The programmable pre-dividers, M and N, and the post-dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency:

F_{OUT} = F_{IN} × N/(M × P)

Where:

P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80

M = 1, 2, 4, 8

N = 32, 40

provided that:

30MHz < (F_{IN} /M) < 40MHz

1200MHz < (F_{OUT} × P) < 1275MHz

The PLL loop bandwidth is user-selectable by external filter components or by using the internal loop filter. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.

The CDCL6010 supports one differential LVDS clock input and a total of 11 differential CML outputs. One output is a straight bypass with no support for jitter cleaning or clock multiplication. The remaining 10 outputs are available in two groups of five outputs each with independent frequency division ratios. Those 10 outputs can be optionally setup to bypass the PLL when no jitter cleaning is needed. The CML outputs are compatible with LVDS receivers if ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL6010 can support a single-ended clock input as outlined in the Pin Description Table

The CDCL6010 can operate as a multi-output clock buffer in a PLL bypass mode.

All device settings are programmable through the SDA/SCL, serial two-wire interface.

The serial interface is 1.8V tolerant only.

The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (*n*) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (*n*) is the same as the post-divide ratio. The phase adjustment step () in time units is given as:

= 1/(n × F_{OUT})

where F_{OUT} is the respective output frequency.

The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C.

The CDCL6010 is available in a 48-pin QFN (RGZ) package.

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