Features for the CDCLVC1310-EVM
- Easy-to-use evaluation board to fan out low phase-noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at 2.5-/3.3-V for VDD and at 1.5-/1.8-/2.5-/3.3-V for VDDO
- Single-ended or differential input clocks or crystal input
Description for the CDCLVC1310-EVM
The CDCLVC1310 is a highly versatile, low jitter and low power clock fan out buffer, which distributes up to ten low jitter LVCMOS clock outputs. The clock is derived from one of three inputs, whose primary and secondary inputs feature differential or single-ended signals and the third input is a crystal input.