The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS
clock outputs with low additive jitter for clock distribution. The input can either be LVDS,
LVPECL, or CML.
The CDCLVD1213 contains a high performance divider for one output (QD) which can divide
the input clock signal by a factor of 1, 2, or 4.
The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part
supports a fail-safe function. The device incorporates an input hysteresis which prevents random
oscillation of the outputs in the absence of an input signal.
The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C
(ambient temperature). The CDCLVD1213 is packaged in small, 16-pin, 3-mm × 3-mm VQFN
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