See datasheet for actual packaging/pinout drawings

Package | PIN:

RHD | 28


I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

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CDCLVD2104RHDT-Low Jitter, Dual 1:4 Universal-to-LVDS Buffer

The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2104 is specifically designed for driving 50- transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical “0”), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.

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