See datasheet for actual packaging/pinout drawings

Package | PIN:

RGE | 24

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

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CDCP1803RGET-1:3 LVPECL Clock Buffer with Programable Divider

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

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