The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency
The CDCS504-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is
either equal to the input frequency or multiplied by the factor of four.
By this, the device can generate output frequencies between 2 MHz and 108 MHz.
A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device
operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP
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