See datasheet for actual packaging/pinout drawings

Package | PIN:

DGG | 48


C (0 to 70)

ECO Plan:

Green (RoHS & no Sb/Br)

TI Store Price:

1 - 9 $ 9.15
10 - 24 $ 8.23
25 - 99 $ 7.68
100 - 249 $ 6.89
250 - 499 $ 6.43
500 - 749 $ 5.60
750 - 999 $ 4.84
1000 - 9999 $ 4.75
  View datasheet for CDCV857BDGG View product folder for CDCV857BDGG

Adjust your quantity during checkout

CDCV857BDGG-2.5 V Phase Lock Loop DDR Clock Driver

The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, theoutputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.

When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857B is characterized for both commercial and industrial temperature ranges.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00