See datasheet for actual packaging/pinout drawings

Package | PIN:

PW | 24


S (0 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

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CDCVF2510APW-3.3-V Phase-Lock Loop Clock Driver with Power Down Mode

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCC and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state.

Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.

The CDCVF2510A is characterized for operation from 0°C to 85°C.

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