The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A
is designed for high-speed digital data transmission in wired and wireless communication systems,
high-frequency direct-digital synthesis (DDS), and waveform reconstruction in test and measurement
applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate
frequencies, which makes the DAC5675A well-suited for multicarrier transmission in TDMA- and
CDMA-based cellular base transceiver stations (BTSs).
The DAC5675A operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A
provides a nominal full-scale differential current output of 20mA, supporting both single-ended and
differential applications. The output current can be directly fed to the load with no additional
external output buffer required. The output is referred to the analog supply voltage
The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for
high-speed digital data input. LVDS features a low differential voltage swing with a low constant
power consumption across frequency, allowing for high-speed data transmission with low noise
levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in
low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing
between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A
current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A has been specifically designed for a differential transformer-coupled output
with a 50 Ω doubly- terminated load. With the 20 mA full-scale output current, both a 4:1 impedance
ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) are
supported. The last configuration is preferred for optimum performance at high output frequencies
and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from
AVDD –1 to AVDD + 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier
allows the user to adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain
range control capabilities. Alternatively, an external reference voltage may be applied. The
DAC5675A features a SLEEP mode, which reduces the standby power to approximately 18 mW.
The DAC5675A is available in a 48-pin HTQFP thermally-enhanced PowerPad package. This
package increases thermal efficiency in a standard size IC package. The device is characterized for
operation over the industrial temperature range of –40°C to +85°C.
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