Features for the DP83867ERGZ-S-EVM
- 1000 Base-Tx IEEE 802.3 Compliant
- Meets EN55011 3m Class B Emissions and Immunity requirements
- SFD IEEE 1588 timestamp
- Wake-on-LAN
- Low power modes: Active Sleep, Passive Sleep, IEEE Power Down, and Deep Power Down
Description for the DP83867ERGZ-S-EVM
The DP83867ERGZ-S-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports SGMII MAC interface.
The DP83867 EVM includes three onboard status LEDs, 5V connectors with onboard LDOs, and is JTAG accessible. The DP83867 EVM is capable of providing a 125MHz reference clock from an onboard 25MHz crystal. Serial management interface, MDIO/MDC, is supported and can be used to access PHY registers for additional features. There are 4-level straps, which allow for system configurations without the need to directly access PHY registers. External power supplies can be connected to each specified voltage rail for additional system evaluation. The DP83867 EVM supports Wake-on-LAN, Start of Frame Detect IEEE 1588 Time Stamp and configurable I/O voltages.