Features for the DP83867IRPAP-EVM
- 1000BASE-TX IEEE 802.3 compliant
- GMII, RGMII & MII MAC interfaces
- SFD IEEE 1588 timestamp
- Low-power modes: Active sleep, passive sleep, IEEE power down and deep power down
- Wake-on-LAN
- Energy-efficient Ethernet
- Support error free data transfer over 125 m on CAT5 cable
Description for the DP83867IRPAP-EVM
The DP83867IRPAP-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports GMII, RGMII and MII MAC interfaces.
The DP83867IRPAP-EVM incudes four onboard status LEDs and a 5-V jack with onboard LDO regulators. The EVM is JTAG accessible and can provide a 125-MHz reference clock from an onboard 25-MHz crystal. The serial management interface, MDIO, is supported and can be used to access the PHY registers for additional features. The 4-level straps let you configure the system without the need to directly access the PHY registers. External power supplies can be connected to each specified voltage rail for additional system evaluation. The DP83867IRPAP-EVM supports energy-efficient Ethernet, wake-on-LAN, start-of-frame detect IEEE 1588 timestamp and configurable I/O voltages.