See datasheet for actual packaging/pinout drawings

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DP83867IRPAP-EVM-DP83867IRPAP-EVM Evaluation Module

The DP83867IRPAP-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports GMII, RGMII and MII MAC interfaces.

The DP83867IRPAP-EVM incudes four onboard status LEDs, 5V jack with onboard LDOs, and is JTAG accessible. The DP83867IRPAP-EVM is capable of providing a 125MHz reference clock from an onboard 25MHz crystal. Serial management interface, MDIO, is supported and can be used to access PHY registers for additional features. There are 4-level straps, which allow for system configurations without the need to directly accessing PHY registers. External power supplies can be connected to each specified voltage rail for additional system evaluation. The DP83867IRPAP-EVM supports Energy Efficient Ethernet, Wake-on-LAN, Start of Frame Detect IEEE 1588 timestamp and configurable I/O voltages.

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