The DS110DF410 is a four channel retimer with integrated signal conditioning. The device
includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision
Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to
enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve
BER < 1×1015.
Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated
sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25-MHz crystal
oscillator clock is used to speed up the CDR lock process. This clock is not used for training the
PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be
loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time
measurement of high-speed serial data for system bring-up or field tuning.
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