The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data
streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output
clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1
phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and
converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS
input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848
The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data
valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip
OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended
for this device.
Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1
receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found
in the Application Information section.
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