The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data transmission over a single differential pair.
The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward
channel and bidirectional control channel data paths. The serializer and deserializer pair is
targeted for connections between imagers and video processors in an electronic control unit (ECU).
This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus
two synchronization signals along with bidirectional control channel bus.
There is a multiplexer at the deserializer to choose between two input imagers. The
deserializer can have only one active input imager. The primary video transport converts 10- and
12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional
control channel transport that accepts control information from an I2C
port and is independent of video blanking period.
Using TI’s embedded-clock technology allows transparent full-duplex communication over a
single differential pair, carrying asymmetrical bidirectional control channel information in both
directions. This single serial stream simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data and clock paths. This significantly
saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and
pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss
from the media over longer distances. Internal DC-balanced encoding and decoding is used to support
AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer
is offered in a 48-pin WQFN package.
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