The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent
data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is
ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS,
VS, DE + three additional general-purpose data channels. This single serial stream simplifies
transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between
parallel data and clock paths. The device saves system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link
II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial
transmission path. By optimizing the Serializer output edge rate for the operating frequency range,
EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances
using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled
interconnects. Using TIs proprietary random lock, the parallel data of the Serializer are
randomized to the Deserializer without the need of REFCLK.
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