The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit
parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream
simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew
problems between parallel data and clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback
feature enables the user to check the integrity of the serial data transmission paths of the
transmitter and receiver while deserializing the serial data to parallel data at the receiver
outputs. The local loopback feature enables the user to check the integrity of the transceiver from
the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides
a low power and low noise environment for reliably transferring data over a serial transmission
path. The equal and opposite currents through the differential data path control EMI by coupling
the resulting fringing fields together.
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