The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock
LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or
backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data
channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into
a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer
Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The
Deserializer automatically locks to incoming data without an external reference clock or special
sync patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including signal conditioning functions,
the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design
effort and lower cable/connector cost for a wide variety of video, control and imaging
applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system
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