The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed
forward channel and a full-duplex control channel for data transmission over a single differential
pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and
bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for
direct connections between graphics host controller and displays modules. This chipset is ideally
suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE)
along with a bi-directional back channel control bus. The primary transport converts 21 bit data
over a single high-speed serial stream, along with a separate low latency bi-directional back
channel transport that accepts control information from an I2C port. Using TI’s embedded clock
technology allows transparent full-duplex communication over a single differential pair, carrying
asymmetrical bi-directional back channel control information in both directions. This single serial
stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew
problems between parallel data and clock paths. This significantly saves system cost by narrowing
data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the
media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled
A sleep function provides a power-savings mode when the high speed forward channel and
embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a
48-pin WQFN packages.
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