The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent
data/control LVDS serial stream with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems
between parallel data and clock paths. It saves system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a
low power and low noise environment for reliably transferring data over a serial transmission path.
By optimizing the serializer output edge rate for the operating frequency range EMI is further
In addition the device features pre-emphasis to boost signals over longer distances using
lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled
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