Features for the LMK04821EVM
- JEDEC JESD204B support to generate pulsed SYSREF.
- Evaluation board configurable using CodeLoader software.
- Accepts differential or single-ended/LVCMOS input clock
- LVPECL outputs can be connected with balun to test equipment or single-ended by using 50-ohm termination on unconnected output.
Description for the LMK04821EVM
The LMK04821EVM supports the LMK0482x family of products, the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual loop PLLatinum™ architecture enables sub-100 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO).
122.88 MHz VCXO comes pre-installed. User may swap out VCXO for own custom VCXO or connect via SMA connectors.
Normally internal VCO is used PLL2, however a footprint exists for external VCO or may connect external VCO via SMA connectors.
PLL loop filters come pre-designed for default case. If changing VCXO or VCO or other operating parameters, loop filter may be redesigned. The Clock Design Tool or the WEBENCH Clock Architect can be used for re-designing loop filter.