See datasheet for actual packaging/pinout drawings

Package | PIN:

SIA | 6

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

TI Store Price:

Qty.Price
1 - 9 $ 21.98
10 - 24 $ 20.43
25 - 99 $ 19.72
100 - 249 $ 17.23
250 - 499 $ 16.39
500 - 749 $ 15.09
750 - 999 $ 13.54
1000 - 9999 $ 13.50
  View datasheet for LMK61E07-SIAT View product folder for LMK61E07-SIAT

Adjust your quantity during checkout

LMK61E07-SIAT-Ultra-Low Jitter Programmable Oscillator with Internal EEPROM

The LMK61E07 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E07 can be configured as LVPECL, LVDS, or HCSL. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00