See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

SIA | 8

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

LMK61E0M-SIAT


Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

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Texas Instruments LMK61E0M-SIAT

The LMK61E0 family of ultra-low jitter PLLatinum™ programmable oscillators utilize fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self startup from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system via I2C serial interface. The device provides fine and coarse frequency margining control via I2C serial interface, making it a digitally controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2ppb using a PFD of 100MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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