The LMK61E2 device is an ultra-low jitter PLLatinum
programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that
generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.
The device features self start-up from on-chip EEPROM that is factory programmed to
generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable
in-system through I2C serial interface. Internal power conditioning
provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the
power delivery network. The device operates from a single 3.3-V ± 5% supply.
The device provides fine and coarse frequency margining options through
I2C serial interface to support system design verification tests (DVT),
such as standard compliance and system timing margin testing.
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