The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin
selectable oscillator that generates commonly used reference clocks. The device is pre-programmed
in factory to support seven unique reference clock frequencies that can be selected by
pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between
LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide
excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power
delivery network. The device operates from a single 3.3 V ± 5% supply.
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