The PC16550D device is an improved version of the original 16450 Universal Asynchronous
Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode: can
also be reset to 16450 Mode under software control) the PC16550D can be put into an alternate mode
(FIFO mode) to relieve the CPU of excessive software overhead.
In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data
per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on
chip to minimize system overhead and maximize system efficiency. Two pin functions have been
changed to allow signalling of DMA transfers.
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from
the CPU. The CPU can read the complete status of the UART at any time during the functional
operation. Status information reported includes the type and condition of the transfer operations
being performed by the UART, as well as any error conditions (parity, overrun, framing, or break
The UART includes a programmable baud rate generator that is capable of dividing the
timing reference clock input by divisors of 1 to (2161), and producing
a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this
16 × clock to drive the receiver logic. The UART has complete MODEM-control capability, and a
processor-interrupt system. Interrupts can be programmed to the users requirements, minimizing the
computing required to handle the communications link.
The UART is fabricated using Texas Instruments advanced
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