The SLK2511C is a single chip multirate transceiver IC used to derive high-speed timing signals for
SONET/SDH based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial
conversion and frame detection function conforming to the SONET/SDH standards.
The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rates through the rate
selection pins or the autorate detection function. An external reference clock operating at 155.52 MHz or
622.08 MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial
The SLK2511C accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at
OC-3, OC-12, OC-24, or OC-48 rates. It also recovers the data and clock from the serial SONET stream and
demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits
that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible
The SLK2511C provides a comprehensive suite of built-in tests for self-test purposes including local and remote
loopback and PRBS (27-1) generation and verification.
The device comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on
the control pins. The SLK2511C is power efficient, dissipating less than 900 mW at 2.488 Gbps, the OC-48 data
rate, and it is characterized for operation from -40°C to 85°C.
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