The SM470R1B1M(3) devices are members of the Texas Instruments SM470R1x family of general-purpose 16-/32-bit reduced
instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high performance
using the high-speed ARM7TDMI 16-/32-bit RISC central processing unit (CPU), resulting in a high
instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16-/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M uses the
big-endian format where the most significant byte of a word is stored at the lowest numbered byte
and the least significant byte of a word is stored at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers
while maintaining low costs. The B1M RISC core architecture offers solutions to these performance
and cost demands while maintaining low power consumption.
The B1M devices contain the following:
- ARM7TDMI 16-/32-bit RISC CPU
- SM470R1x system module (SYS) with 470+ enhancements
- 1MB flash
- 64KB SRAM
- ZPLL clock module
- DWD timer
- AWD timer
- Enhanced RTI module
- JTAG security module
- Two SPI modules
- Three SCI modules
- Two HECC
- Five I2C modules
- 10-bit MibADC, with 12 input channels
- HET controlling 12 I/Os
- Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
- Address decoding
- Memory protection
- Memory and peripherals bus supervision
- Reset and abort exception management
- Prioritization for all internal interrupt sources
- Device clock control
- Parallel signature analysis (PSA)
The enhanced RTI module on the B1M has the option to be driven by the oscillator
clock. The DWD is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and
peripheral select assignment, interrupt priority, and a device memory map. For a more detailed
functional description of the SYS module, see the TMS470R1x System Module Reference Guide (SPNU189).
The B1M memory includes general-purpose SRAM supporting single-cycle read/write
accesses in byte, half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable, and
programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a
system clock frequency of up to 24 MHz or 30 MHz, depending on the input voltage. When in pipeline
mode, the flash operates with a system clock frequency of up to 48 MHz or 60 MHz, depending on the
input voltage. For more detailed information on the flash, see 184.108.40.206.
The MSM and the JTAG security module prevent unauthorized access and visibility to
on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.
The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs,
and five I2Cs. The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type devices. The SCI is a
full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other
peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial, multimaster
communication protocol that efficiently supports distributed realtime control with robust
communication rates of up to 1 Mbps. These CAN peripherals are ideal for applications operating in
noisy and harsh environments (for example, industrial fields) that require reliable serial
communication or multiplexed wiring. The I2C module is a multimaster
communication module providing an interface between the B1M microcontroller and an
I2C-compatible device through the I2C serial
bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more
detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference
guides (SPNU195, SPNU196, and SPNU197). For more
detailed functional information on the I2C, see the TMS470R1x Inter-
Integrated Circuit (I2C) Reference Guide
The HET is an advanced intelligent timer that provides sophisticated timing functions
for realtime applications. The timer is software-controlled, using a reduced instruction set, with
a specialized timer micromachine and an attached I/O port. The HET can be used for compare,
capture, or general-purpose I/O. It is especially well-suited for applications requiring multiple
sensor information and drive actuators with complex and accurate time pulses. The HET used in this
device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more
detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).
The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent
HET high-resolution channels to be XORed together, making it possible to output smaller pulses than
a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer
(HET) Reference Guide (SPNU199).
The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC
channels can be converted individually or can be grouped by software for sequential conversion
sequences. There are three separate groupings, two of which can be triggered by an external event.
Each sequence can be converted once when triggered or configured for continuous conversion mode.
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter
(MibADC) Reference Guide (SPNU206).
The ZPLL clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1 to 8). The function of the ZPLL is
to multiply the external frequency reference to a higher frequency for internal use. The ZPLL
provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock
(SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock
(ICLK) to all other B1M device modules. For more detailed functional information on the ZPLL, see
the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (SPNU212).
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The EBM is a standalone module that supports the multiplexing of the GIO functions and
the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM)
Reference Guide (SPNU222).
The B1M device also has an external clock prescaler (ECP) module that when enabled,
outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a
user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed
functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (SPNU202).
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