See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

ZQE | 64

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

SN65DSI83ZQER


Single-Channel MIPI® DSI to Single-Link FlatLink™ LVDS Bridge

TI Store Price:

 
 
Qty.Price
1 - 9 $ 4.10
10 - 24 $ 3.69
25 - 99 $ 3.43
100 - 249 $ 3.01
250 - 499 $ 2.82
500 - 749 $ 2.40
750 - 999 $ 2.02
1000 - 9999 $ 1.70

Adjust your quantity during checkout

Texas Instruments SN65DSI83ZQER

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm BGA MICROSTAR JUNIOR at 0.5-mm pitch package, and operates across a temperature range from –40ºC to 85ºC.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00