The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver
front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input
bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and
converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel
clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with
four data lanes per link.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24
bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch
between the DSI and LVDS interfaces.
Designed with industry compliant interface technology, the SN65DSI84 is compatible with a
wide range of micro-processors, and is designed with a range of power management features including
low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI84 is implemented in a small outline 5x5mm BGA at 0.5 mm pitch package, and
operates across a temperature range from 40°C to 85°C.
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