The SN65LVDS302 receiver de-serializes FlatLink™3G compliant serial input data to 27
parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1,
2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS
outputs after checking the parity bit. If the parity check confirms correct parity, the Channel
Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a
high pulse while the data output bus disregards the newly-received pixel. Instead, the last data
word is held on the output bus for another clock cycle.
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