The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output
links. The device pinout is optimized to interface with the OMAP3630 application processor. The
device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS
input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the
27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits.
The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented.
The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10
times the pixel clock data rate. A copy of the pixel clock is output on an additional differential
output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling
(SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to
When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an
internal high-speed clock at the line rate of the data lines. The parallel data is latched on the
rising edge of PCLK. The serialized data is presented on the serial outputs D0, D1, D2 with a
recreation of the Pixel clock PCLK generated from the internal high-speed clock and output on the
CLK output. If the input clock PCLK stops, the device enters a standby mode to conserve
Two Link-Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The
TXEN input may be used to put the SN65LVDS311 in a shutdown mode. The SN65LVDS311 enters an active
Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for
controlling an external pin. The SN65LVDS311 is characterized for operation over ambient air
temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage
during power-up and to avoid current flow into the device inputs during power-up.
View datasheet View product folder