See datasheet for actual packaging/pinout drawings

Package | PIN:

ZQL | 59


I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

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SN65LVDS324ZQLR-High Definition Image Sensor Receiver

The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR clock by a ratio, and outputs parallel CMOS 1.8 V data on the rising clock edge. It bridges the video stream interface between HD image sensors made by leading manufacturers, to a format that common processors can accept. The supported pixel frequency is 18.5 MHz to 162 MHz — suitable for resolutions from VGA to 1080p60.

Four high-level modes are supported:
Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel 2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.

The SN65LVDS324 is configured through its I2C-programmable registers. This volatile memory must be written after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max allowable frame size is 8191 x 8191.

With integrated differential input termination, and a footprint of 4.5 × 7mm, the SN65LVDS324 provides a differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range of –40°C to 85°C.

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