These 18-bit universal bus transceivers consist of storage
elements that can operate either as D-type latches or D-type
flip-flops to allow data flow in transparent or clocked modes.
Data flow in each direction is controlled by output-enable (OEAB
and ), latch-enable
(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data
flow, the device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at a high or
low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is
high, the outputs are active. When OEAB is low, the outputs are in
the high-impedance state.
Data flow for B to A is similar to that of A to B but uses, LEBA, and CLKBA. The output
enables are complementary (OEAB is active high and is active low).
To ensure the high-impedance state during power up or power down,
OE should be tied to GND through a pulldown resistor and should be tied to VCC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sourcing/current-sinking capability of the
The SN54ABT16501 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74ABT16501 is characterized for operation from -40°C to
View datasheet View product folder