See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

PM | 64

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

SN74ABT18504PM


Scan Test Devices With 20-Bit Universal Bus Transceivers

TI Store Price:

 
 
Qty.Price
1 - 9 $ 16.96
10 - 24 $ 15.28
25 - 99 $ 14.64
100 - 249 $ 12.88
250 - 499 $ 12.32
500 - 749 $ 11.36
750 - 999 $ 10.24
1000 - 9999 $ 9.41

Adjust your quantity during checkout

Texas Instruments SN74ABT18504PM

The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the , LEBA, , and CLKBA inputs.

In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface.

Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

The SN54ABT18504 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18504 is characterized for operation from -40°C to 85°C.

View datasheet
View product folder
Order SummaryEdit >
Subtotal: $0.00
Shipping & Handling: -
Total (USD): $0.00