These octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
When the output-enable (OE)\ is low, the device passes noninverted data from the A bus to the B bus or from
the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. A high on (OE)\ disables
the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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