The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds
an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate
clocks are provided for both the shift and storage registers. The shift register has a direct
overriding clear (SRCLR) input, a serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except
QH′ are in the high-impedance state.
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