See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

DRY | 6

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

SN74AUP1G126DRYR


Low-Power Single Bus Buffer Gate with 3-State Output

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Texas Instruments SN74AUP1G126DRYR

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity ).

This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals.

To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

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