See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

D | 16

Temp:

C (0 to 70)

ECO Plan:

Green (RoHS & no Sb/Br)

SN74F112DR


Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

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Texas Instruments SN74F112DR

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C.

 

 

 

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