See datasheet for actual packaging/pinout drawings

Packaging

Package | PIN:

DGG | 64

Temp:

I (-40 to 85)

ECO Plan:

Green (RoHS & no Sb/Br)

SN74GTL1655DGGR


16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live Insertion

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Texas Instruments SN74GTL1655DGGR

The SN74GTL1655 is a high-drive (100 mA), low-output-impedance (12 ) 16-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 8-bit transceivers and combines D-type flip-flops and D-type latches to allow for transparent, latched, and clocked modes of data transfer similar to the ’16501 function. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching.

The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels but are not 5-V tolerant. VREF is the reference input voltage for the B port.

This device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals, but with a common clock and output enable inputs for both transceiver words.

Data flow for each word is determined by the respective latch enables (LEAB and LEBA), output enables (OEAB\ and OEBA\), and clock (CLK). The output enables (1OEAB\, 1OEBA\, 2OEAB\, and 2OEBA\) control byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK low-to-high transition. When OEAB\ is low, the outputs are active. With OEAB\ high, the outputs are in the high-impedance state.

Data flow for the B-to-A direction is identical, but uses OEBA\, LEBA, and CLK. Note that CLK is common to both directions and both 8-bit words. (OE)\ is also common and is used to disable all I/O ports simultaneously.

The SN74GTL1655 has adjustable edge-rate control (VERC ). Changing VERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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